- Created on Sunday, 06 October 2013 16:17
- Last Updated on Tuesday, 08 October 2013 02:08
When developing programmable logic for the DE0 Nano Education and Development Board a SRAM object file (.sof), containing a configuration bit stream, is typically used to configure the hosted Cyclone IV FPGA at runtime, using the built-in USB Blaster.
When the programmable logic development stage has been completed the resultant configuration data can be downloaded to a configuration device, which reconfigures the Cyclone IV FPGA on power-on or reset. How the configuration data is loaded onto the configuration device is the focus of this article.
Configuration Scheme Summary
In this section a brief introduction to the DE0 Nano configuration scheme is presented. For a more detailed introduction please see the references at the end of this article. The Cyclone IV FPGA on the DE0 Nano is connected to a 16Mb configuration device, the EPCS64, which is used to host the configuration bit stream. A typical connection between a serial configuration device and a Cyclone IV FPGA can be seen, in Figure TBD, below.
Figure 1: A typical Cyclone IV Configuration Scheme. Taken from Configuration and Remote System Upgrades in Cyclone IV Devices datasheet, Altera Corp, May 2013.
A clue to the exact configuration scheme used on the DE0 Nano can be found by examining the board’s schematic diagram, seen in Figure 2, below. If one assumes DNI stands for Do Not Install then the Cyclone IV is configured in the Active Serial (AS) mode, as the MSEL0 and MSEL2 pins are set to a logic level 1 and MSEL1 is set at a logic level of zero.
Figure 2: The Cyclone IV configuration scheme used on the DE0 Nano Development Board.
So what does the active serial mode do for us over other modes? In this particular 1-bit mode the Cyclone IV acts as the configuration master and the EPCS device acts as the configuration slave. Why use this scheme and not one of the others? An answer to this question and probably others is outside the scope of this article, but may form the basis of another article. For now we will just get on and describe what most of you have visited this page to learn!
Configuration Scheme Summary
Figure 3: In Quartus generate the SRAM object file (.sof), in the usual manner, by compiling your design. Then select "File->Convert Programming File" in the File menu.
Figure 4: Next, in the Dialog that appears under the "Output Programming File" section set the "Programming File Type" to JTAG Indirect Configuration File (.jic).
Figure 5:Set the configuration device to EPCS64, the one on the DE0 Nano Development Board.
Figure 6: Next, you need to provide a "File name". I provided an appropriate one, but left the output_files directory as the output folder, for consistency.
Figure 7: Next, in the "Input Files to Convert" section click on "Add Device". In the select devices dialog that appears set the device family to Cyclone IV and the device name as EP4CE22. Then click the "OK" button.
Figure 8: Now, you should see the EP4CE22 device under the File/Data area column. Next, click on the "SOF Data" item and then on the "Add File" button. Navigate to the .sof file created previously and add it.
Figure 9: The result can be seen in the image above. Without considering any of the other options or "Advanced "Setting" we are ready to go! Click on the "Generate" button.
Figure 10: Navigate back to Quartus' programming tool by, in Quartus, selecting "Tools->Programmer". Delete any existing entries and in the left hand panel select "Add Files..
Figure 11: A "Select Programming File" dialog should appear. Select the JTAG indirect programming file (.jic) generated in the previous steps.
Figure 12: Your Programming dialog should now look similar to the one above. Click on the "Program/Configure" check box. Then click the "Start" button. Finally, when the progress bar reports 100% success, recycle the power on the DE0 Nano by removing the USB cable and plugging it in again and your done. Well done!
- Configuration and Remote System Upgrades in Cyclone IV Devices datasheet, Altera Corp, May 2013.
- DE0 Nano Schematics, Terasic Technologies, Inc. October, 2011.