Actel (now Microsemi) offer a range of non-volatile, FLASH-centric FPGAs. A set of tutorials about programming, configuring and understanding, in general, Field Programmable Gate Arrays (FPGAs) can be found here. Eventually, the development of an Actel DIP module development board will also be found here.
- Created on Saturday, 05 March 2011 10:24
- Last Updated on Friday, 02 September 2011 15:54
This brief tutorial derives the typical set up used to drive the synchronous logic within the ProASIC3 FPGA from Actel, in the PQ208 package, with an external oscillator. In the system-level diagram, shown above, the external oscillator is the labelled item (1). The chosen global input pin, (2), allows connection to the Clock Conditioning Circuit (CCC). The CCC, with integrated Phase Lock Loop (PLL), item(3), allows frequency synthesis of the clock input source. A separate power supply input, for the PLL, item (4), provides the analog power supply isolation from unwanted digital I/O switching noise.